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NXP Semiconductors /LPC408x_7x /EMC /CONFIG

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Interpret as CONFIG

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (LITTLEENDIAN)EM 0RESERVED0 (PORRESET)CLKR 0RESERVED

EM=LITTLEENDIAN, CLKR=PORRESET

Description

Configures operation of the memory controller

Fields

EM

Endian mode. On power-on reset, the value of the endian bit is 0. All data must be flushed in the EMC before switching between little-endian and big-endian modes.

0 (LITTLEENDIAN): Little-endian mode (POR reset value).

1 (BIGENDIAN): Big-endian mode.
RESERVED

Reserved. Read value is undefined, only zero should be written.
CLKR

CCLK: CLKOUT ratio. This bit must contain 0 for proper operation of the EMC.

0 (PORRESET): 1:1(POR reset value)

1 (DONOTUSE): 1:2 (this option is not available on the LPC178x/177x)
RESERVED

Reserved. Read value is undefined, only zero should be written.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data